Modern computing systems utilize various hardware and software techniques to detect internal data errors. One such technique used within RAID I/O devices includes multiple redundant central processing units (CPUs) to duplicate processing. The results are compared and, if identical, a decision is made as to whether the data is error-free. If errors are detected, a decision is made as to which of the redundant devices is correct.
In RISC processors, redundant processing cores are sometimes implemented on a common die to similarly provide redundant error checking techniques. Redundancy may also be duplicated at lower level devices (e.g., an ALU) to provide like error-detect capabilities for parity level decisions. RISC processors also sometimes implement error correction code such as in connection with cache entries. However, data errors within the random and speculative logic of RISC processors are particularly difficult to detect; and there are no practical error correction techniques suitable for operations such as prefetch, branch prediction and bypassing.
There may be many causes of data errors within RISC processors. By way of example, cosmic ray particles may flip a bit within a logical latch of the processor. Dynamic logic and storage nodes are particularly susceptible to cosmic and alpha particles that perturb internal storage cells. Even static logic devices (e.g., NOR gates) may exhibit error or noise due to cosmic particles.
Accordingly, prior art techniques exist that may “detect” logical errors and the like within RISC processors. Nevertheless, redundant detection techniques often complicate timing and bypass logic; it may for example take up to three extra cycles to perform a compare between redundant devices, which greatly complicates the write-back logic of parallel pipelines.
Moreover, within the prior art, the “recovery” associated with data errors is quite difficult and cumbersome. Often, for example, this recovery involves analyzing and electing which of two redundant devices to use as the appropriate data. The prior art has even implemented three redundant devices to help this analysis and election. Improvements are thus needed to facilitate data recovery in the event of logical errors in modem processors. One feature of the invention is to provide recovery logic within the RISC processor to recapture lost or corrupted data written to register files. Other features of the invention are apparent within the description that follows.